The present invention provides a circuit and method for reducing skew between a clock signal and a reference signal. Specifically, the circuit and method reduces the skew between a reference signal and the clock signal produced from a phase lock loop which utilizes the reference signal.
Radio frequency communication systems utilize phase lock loop (PLL) circuits to produce a clock signal which control digital devices such as frequency synthesizers and digital to analog conversion circuits. The well known PLL circuit receives a reference signal and generates from a voltage controlled oscillator (VCO) a higher power clock signal which is phase and frequency locked to the reference signal.
In higher frequency applications above 1-GHz, a time delay exists between the reference signal and the VCO output signal which is referred to as skew. The skew can produce errors in the analog to digital conversion process, as well as reduce system performance in base station communications operations. The skew is a result of dynamic mismatches between circuit elements of the phase lock loop. Specifically, mismatches of transistors forming the phase detector and charge pump which establishes a control voltage for the voltage controlled oscillator introduce a phase error between the input reference signal and the VCO signal.
In applications which require the conversion of digital signals to analog signals, a slight clock skew will contribute significantly to the noise in a high resolution digital to analog converters. Even when the passive and active elements in the phase lock loop are matched, at 2-GHz a clock skew of 30 PS may still exist between the reference signal and VCO signal.
The prior art includes various techniques for reducing clock skew for a multi-channel signal source. U.S. Pat. No. 5,384,781 describes a cross-coupled flip-flop calibration circuit and microprocessor which aligns the timing of a pair of signals from a multi-channel signal source. The flip-flop calibration circuit indicates which of a pair of signals is leading in phase, and the microprocessor uses the output of the flip-flop circuit to adjust a signal delay for one of the signal sources. By changing the delay of the leading signal, a calibrated value can be obtained wherein both signals have essentially the same timing.
U.S. Pat. No. 5,394,024 provides a circuit for eliminating off chip to on chip clock skew. An on chip clock signal is derived by phase delaying an off chip generated clock signal. First and second delay paths are connected to receive the off chip clock signal. A phase detector and filter circuit generates control signals to adjust the respective phase delay through each of the delay paths. A multiplexer selects one of the delay paths to produce the on chip clock signal.
The present invention is directed to providing a method for calibrating a VCO generated signal with respect to a sine wave reference signal to reduce the skew between the VCO signal and the sine reference signal of the phase lock loop.
An apparatus and method are provided for correcting clock signal skew. A calibration circuit comprising a skew compensator is connected to receive an uncorrected clock signal, and delays the clock signal in accordance with a skew control voltage. The skew control voltage is derived from the signal to noise ratio of an analog signal produced from a device controlled by the clock signal. In a preferred embodiment of the invention, a digital analog converter produces a signal to noise ratio measurement signal which is representative of the skew of the clock signal. The signal to noise ratio signal is supplied as a control signal to a skew compensator, which affectively delays the clock signal in accordance with the applied control signal. The clock signal is shifted in time to produce a signal to noise ratio signal having a minimum value, representing a zero skew condition.
In accordance with a preferred embodiment of the invention, a source of sine wave reference signals is used in a sine digital to analog converter. The digital to analog converter produces Sine pulses having an area representing the value of a digital input signal. A signal representing the signal to noise ratio of the analog signal is produced from the digital to analog converter, representing the skew between an input clock signal and the sine wave reference signal. A skew controller receives the signal to noise ratio signal and generates the control signal for a variable delay network. The variable delay network delays the input signal in accordance with the signal to noise ratio signal derived from the digital to analog converter to eliminate the clock skew.